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? 1999,2000 mos integrated circuit pd16681a lcd controller/driver for dot matrix display of jis level 1 and jis level 2 kanji sets data sheet document no. s14207ej3v0ds00 (3rd edition) date published june 2002 ns cp(k) printed in japan the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. description the pd16681a is a single-chip controller driver that can display japanese text; including jis level 1 kanji, jis level 2 kanji, hiragana, and katakana. each chip can display up to four lines containing up to eight full width characters (11 x 12 dots), or up to four lines containing up to 16 half width characters (5 x 12 dots), as well 96 pictographs. features ? lcd controller/driver for dot matrix display of jis level 1 and jis level 2 kanji sets ? on-chip rom for character generation ? jis level 1 + level 2 kanji (11 x 12 dots): 6,355 characters ? jis non-kanji characters (11 x 12 dots): 453 characters ? half width alphanumeric characters (5 x 12 dots): 192 characters ? on-chip ram for character generation ? 8 types (12 x 13 dots) ? on-chip boost circuit: switchable between 3x and 4x modes ? ram for pictograph data displays: 96 bits ? outputs: 96 segments, 52 commons ? duty settings: 1/39 or 1/52 ? switchable data inputs: serial or 8-bit parallel ? on-chip divider resistor ? selectable bias settings (1/8 bias, 1/7 bias, or 1/6 bias) ? on-chip oscillation circuit ordering information part number package rom code pd16681a-001 wafer standard pd16681ap-001 chip (cog compliant) standard remark purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives.
data sheet s14207ej3v0ds 2 pd16681a 1. block diagram i/o buffer ram data register index register control register ram address counter display data ram timing generator pictograph data ram character generator ram full-width character generator rom half-width character generator rom address formation circuit display attribute control circuit cursor control circuit parallel/serial conversion circuit smooth scroll control circuit 96 bits shift register 96 bits latch circuit segment driver oscillation circuit common driver 66 12 6 6 8 7 8 8 8 4 8 3 dc/dc converter op amp. d/a converter lcd voltage generator 6 8 v lc1 v lc2 c 1 , c 1 stb ws e/sck test out /reset seg inv com inv com 1 to com 51 pcom 1 ,pcom 2 osc in osc out osc bri c 2 , c 2 c 3 , c 3 v ext seg 1 to seg 96 amp in(+) amp in( ? ) amp out amp cha v lcbs1 v lc3 v lcbs2 v lcbs3 v lc4 v lc5 v dd v ss d 0 / data d 1 to d 7 + ? + + ? ? v lcd da cha remark /xxx indicates active low si gnals.
data sheet s14207ej3v0ds 3 pd16681a 2. pin configuration (pad layout) chip size: 2.80 x 10.48 mm 2 241 219 218 108 107 83 82 1 y x
data sheet s14207ej3v0ds 4 pd16681a table 2-1. pad layout pad no. pin name x ( m) y ( m) pad no. pin name x ( m) y ( m) pad no. pin name x ( m) y ( m) pad no. pin name x ( m) y ( m) 1 dummy1 ? 1273 4800 61 da cha ? 1273 ? 2400 121 seg 90 1273 ? 3735 181 seg 30 1273 1665 2v lcbs1 ? 1273 4680 62 amp cha ? 1273 ? 2520 122 seg 89 1273 ? 3645 182 seg 29 1273 1755 3v lcbs1 ? 1273 4560 63 seg inv ? 1273 ? 2640 123 seg 88 1273 ? 3555 183 seg 28 1273 1845 4v lcbs2 ? 1273 4440 64 com inv ? 1273 ? 2760 124 seg 87 1273 ? 3465 184 seg 27 1273 1935 5v lcbs2 ? 1273 4320 65 osc in ? 1273 ? 2880 125 seg 86 1273 ? 3375 185 seg 26 1273 2025 6v lcbs3 ? 1273 4200 66 osc out ? 1273 ? 3000 126 seg 85 1273 ? 3285 186 seg 25 1273 2115 7v lcbs3 ? 1273 4080 67 osc bri ? 1273 ? 3120 127 seg 84 1273 ? 3195 187 seg 24 1273 2205 8amp out ? 1273 3960 68 d 0 /data ? 1273 ? 3240 128 seg 83 1273 ? 3105 188 seg 23 1273 2295 9amp out ? 1273 3840 69 d 1 ? 1273 ? 3360 129 seg 82 1273 ? 3015 189 seg 22 1273 2385 10 amp in( ? ) ? 1273 3720 70 d 2 ? 1273 ? 3480 130 seg 81 1273 ? 2925 190 seg 21 1273 2475 11 amp in( ? ) ? 1273 3600 71 d 3 ? 1273 ? 3600 131 seg 80 1273 ? 2835 191 seg 20 1273 2565 12 amp in(+) ? 1273 3480 72 d 4 ? 1273 ? 3720 132 seg 79 1273 ? 2745 192 seg 19 1273 2655 13 amp in(+) ? 1273 3360 73 d 5 ? 1273 ? 3840 133 seg 78 1273 ? 2655 193 seg 18 1273 2745 14 v lc5 ? 1273 3240 74 d 6 ? 1273 ? 3960 134 seg 77 1273 ? 2565 194 seg 17 1273 2835 15 v lc5 ? 1273 3120 75 d 7 ? 1273 ? 4080 135 seg 76 1273 ? 2475 195 seg 16 1273 2925 16 v lc5 ? 1273 3000 76 ws ? 1273 ? 4200 136 seg 75 1273 ? 2385 196 seg 15 1273 3015 17 v lc4 ? 1273 2880 77 stb ? 1273 ? 4320 137 seg 74 1273 ? 2295 197 seg 14 1273 3105 18 v lc4 ? 1273 2760 78 e/sck ? 1273 ? 4440 138 seg 73 1273 ? 2205 198 seg 13 1273 3195 19 v lc4 ? 1273 2640 79 /r eset ? 1273 ? 4560 139 seg 72 1273 ? 2115 199 seg 12 1273 3285 20 v lc3 ? 1273 2520 80 test out ? 1273 ? 4680 140 seg 71 1273 ? 2025 200 seg 11 1273 3375 21 v lc3 ? 1273 2400 81 dummy2 ? 1273 ? 4800 141 seg 70 1273 ? 1935 201 seg 10 1273 3465 22 v lc3 ? 1273 2280 82 dummy3 ? 1273 ? 4920 142 seg 69 1273 ? 1845 202 seg 9 1273 3555 23 v lc2 ? 1273 2160 83 dummy4 ? 1120 ? 5113 143 seg 68 1273 ? 1755 203 seg 8 1273 3645 24 v lc2 ? 1273 2040 84 dummy5 ? 1030 ? 5113 144 seg 67 1273 ? 1665 204 seg 7 1273 3735 25 v lc2 ? 1273 1920 85 com 27 ? 940 ? 5113 145 seg 66 1273 ? 1575 205 seg 6 1273 3825 26 v lc1 ? 1273 1800 86 com 28 ? 850 ? 5113 146 seg 65 1273 ? 1485 206 seg 5 1273 3915 27 v lc1 ? 1273 1680 87 com 29 ? 760 ? 5113 147 seg 64 1273 ? 1395 207 seg 4 1273 4005 28 v lc1 ? 1273 1560 88 com 30 ? 670 ? 5113 148 seg 63 1273 ? 1305 208 seg 3 1273 4095 29 v lcd ? 1273 1440 89 com 31 ? 580 ? 5113 149 seg 62 1273 ? 1215 209 seg 2 1273 4185 30 v lcd ? 1273 1320 90 com 32 ? 490 ? 5113 150 seg 61 1273 ? 1125 210 seg 1 1273 4275 31 v lcd ? 1273 1200 91 com 33 ? 400 ? 5113 151 seg 60 1273 ? 1035 211 com 26 1273 4365 32 c 1 + ? 1273 1080 92 com 34 ? 310 ? 5113 152 seg 59 1273 ? 945 212 com 25 1273 4455 33 c 1 + ? 1273 960 93 com 35 ? 220 ? 5113 153 seg 58 1273 ? 855 213 com 24 1273 4545 34 c 1 + ? 1273 840 94 com 36 ? 130 ? 5113 154 seg 57 1273 ? 765 214 com 23 1273 4635 35 c 1 ? ? 1273 720 95 com 37 ? 40 ? 5113 155 seg 56 1273 ? 675 215 com 22 1273 4725 36 c 1 ? ? 1273 600 96 com 38 50 ? 5113 156 seg 55 1273 ? 585 216 com 21 1273 4815 37 c 1 ? ? 1273 480 97 com 39 140 ? 5113 157 seg 54 1273 ? 495 217 dummy10 1273 4905 38 c 2 + ? 1273 360 98 com 40 230 ? 5113 158 seg 53 1273 ? 405 218 dummy11 1273 4995 39 c 2 + ? 1273 240 99 com 41 320 ? 5113 159 seg 52 1273 ? 315 219 dummy12 950 5113 40 c 2 + ? 1273 120 100 com 42 410 ? 5113 160 seg 51 1273 ? 225 220 com 20 860 5113 41 c 2 ? ? 1273 0 101 com 43 500 ? 5113 161 seg 50 1273 ? 135 221 com 19 770 5113 42 c 2 ? ? 1273 ? 120 102 com 44 590 ? 5113 162 seg 49 1273 ? 45 222 com 18 680 5113 43 c 2 ? ? 1273 ? 240 103 com 45 680 ? 5113 163 seg 48 1273 45 223 com 17 590 5113 44 c 3 + ? 1273 ? 360 104 com 46 770 ? 5113 164 seg 47 1273 135 224 com 16 500 5113 45 c 3 + ? 1273 ? 480 105 com 47 860 ? 5113 165 seg 46 1273 225 225 com 15 410 5113 46 c 3 + ? 1273 ? 600 106 dummy6 950 ? 5113 166 seg 45 1273 315 226 com 14 320 5113 47 c 3 ? ? 1273 ? 720 107 dummy7 1040 ? 5113 167 seg 44 1273 405 227 com 13 230 5113 48 c 3 ? ? 1273 ? 840 108 dummy8 1273 ? 4905 168 seg 43 1273 495 228 com 12 140 5113 49 c 3 ? ? 1273 ? 960 109 com 48 1273 ? 4815 169 seg 42 1273 585 229 com 11 50 5113 50 v dd1 ? 1273 ? 1080 110 com 49 1273 ? 4725 170 seg 41 1273 675 230 com 10 ? 40 5113 51 v dd1 ? 1273 ? 1200 111 com 50 1273 ? 4635 171 seg 40 1273 765 231 com 9 ? 130 5113 52 v dd2 ? 1273 ? 1320 112 com 51 1273 ? 4545 172 seg 39 1273 855 232 com 8 ? 220 5113 53 v dd2 ? 1273 ? 1440 113 dummy9 1273 ? 4455 173 seg 38 1273 945 233 com 7 ? 310 5113 54 v dd2 ? 1273 ? 1560 114 pcom 2 1273 ? 4365 174 seg 37 1273 1035 234 com 6 ? 400 5113 55 v ss ? 1273 ? 1680 115 seg 96 1273 ? 4275 175 seg 36 1273 1125 235 com 5 ? 490 5113 56 v ss ? 1273 ? 1800 116 seg 95 1273 ? 4185 176 seg 35 1273 1215 236 com 4 ? 580 5113 57 v ss ? 1273 ? 1920 117 seg 94 1273 ? 4095 177 seg 34 1273 1305 237 com 3 ? 670 5113 58 v ss ? 1273 ? 2040 118 seg 93 1273 ? 4005 178 seg 33 1273 1395 238 com 2 ? 760 5113 59 v ss ? 1273 ? 2160 119 seg 92 1273 ? 3915 179 seg 32 1273 1485 239 com 1 ? 850 5113 60 v ext ? 1273 ? 2280 120 seg 91 1273 ? 3825 180 seg 31 1273 1575 240 pcom 1 ? 940 5113 241 dummy13 ? 1030 5113
data sheet s14207ej3v0ds 5 pd16681a 3. pin functions 3.1 power supply system pins pin symbol pin name pad no. i/o description v dd logic power supply boost circuit power supply 50 to 54 ? power supply pins for logic and boost circuit v ss logic ground driver ground 55 to 59 ? ground pins for logic and driver circuit v lcd driver power supply 29 to 31 ? power supply pins for driver. output pin for internal boost circuit. connect a 1- f capacitor between these pins and the v ss pins for boosting. if not using the internal boost circuit, a direct driver power supply can be input. v lc1 -v lc5 reference power supply pins for driver 14 to 28 ? these are reference power supply pins for the lcd driver. leave these pins open if an internal bias has been selected. connect a capacitor to ground. v lcbs1 -v lcbs3 bias value setting 2 to 7 ? when selecting an internal bias, the bias value can be changed connecting these pins outside of the ic. c 1 + , c 1 - c 2 + , c 2 - c 3 + , c 3 - capacitor connection 32 to 49 ? these are capacitor connection pins for the boost circuit. connect a 1- f capacitor.
data sheet s14207ej3v0ds 6 pd16681a 3.2 logic system pins pin symbol pin name pad no. i/o description ws select word length 76 input use this pin to select the word length. an 8-bit parallel interface is used for high level and a serial interface is used for low level. this setting cannot be changed after the power has been switched on. da cha select d/a converter 61 input use this pin to select whether or not to use the d/a converter for regulating the lcd driver voltage. select high level to use the d/a converter or low level to not use it. stb strobe 77 input this is used for the device?s select signal and strobe signal for communication. communication is initialized at the rising edge or falling edge of stb. command data receive standby status occurs at the falling edge of stb. communication is enabled when stb is low. also, enabled status or the shift clock is ignored when stb is high. e/sck enable/shift clock 78 input this is an input enable pin for data when the parallel interface is used. during the read-in operation, data is captured in the interface buffer at the signal?s rising edge. during a read-out operation, data is read-out from the interface buffer at the signal?s falling edge. when using a serial interface, this pin is used for the data shift clock. during the read-in operation, data is captured in the shift register at the signal?s rising edge. during a read-out operation, data is read from the shift register at the signal?s falling edge. d 0 /data data bus/data 68 i/o this pin is used for data bus bit d 0 when using the parallel interface. when using the serial interface, it is an i/o pin (tri-state) for commands and display data. d 1 -d 7 data bus 69 to 75 i/o these pins are used for data bus bits d 1 to d 7 when using the parallel interface. it should be fixed high or low when using the serial interface. test out test output 80 output this is a test output pin. leave this pin open when using the device. /reset reset 79 input this pin is used for internal resets at low-level. amp cha op amp switch for lcd driver?s power supply level 62 input this pin is used to control the op amp that works with the lcd driver?s power supply level. high-power mode is set when at low level and normal mode is set when at high level. v ext reference power supply switch 60 input this pin is used to select the reference power supply circuit?s supply mode. high level sets external mode and low level sets internal mode. seg inv segment direction switch 63 input this pin is used to control the segment output direction. low level sets forward direction and high level sets reverse direction. com inv common scan direction switch 64 input this pin is used to switch the common scan direction. low level sets forward direction and high level sets reverse direction. osc in oscillator 65 input these pins are connected to a 100-k ? resistance. when using an osc out 66 output external oscillator, input to osc in and leave osc out open. osc bri external clock for blink function 67 input this is an input pin for the 2-hz external clock. internally, it is divided by half to generate a 1-hz signal that is used as the synchronization signal for the blink function.
data sheet s14207ej3v0ds 7 pd16681a 3.3 driver system pins pin symbol pin name pad no. i/o description seg 1 -seg 96 segment 115 to 210 output segment output pins com 1 -com 51 common 85 to 105 109 to 112 211 to 216 220 to 239 output common output pins 1/52 duty : use com 1 to com 51 1/39 duty : use com 1 to com 19 , com 27 to com 45 and leave com 20 to com 26 , com 46 to com 51 open pcom 1 , pcom 2 pictograph common 240, 114 output common output pins for pictographs the same signal is output from pcom 1 and pcom 2 . amp in(+) op amp inputs 10 to 13 input these are input pins for the op amp that regulates the lcd driver voltage. leave the amp in(+) pin unconnected when using the on-chip d/a converter. when not using the d/a converter, a reference voltage must amp in( ? ) be input. connect the amp in( ? ) pin to a resistor used to regulate the lcd voltage. (see diagram below.) amp out op amp outputs 8,9 output these are output pins for the op amp that regulates the lcd driver voltage. normally, they are connected to resistors that are used to regulate the lcd voltage. (see diagram below.) since the amp out pins are used to stabilize the on-chip amp?s output, we recommend connecting them to a capacitor that is rated between 0.1 and 1.0 f. dummy dummy 1, 81 to 84, 106 to 108, 113, 217 to 219, 241 ? dummy pins are not connected to the internal circuit. leave open if they are not used. figure 3 ? ? ? ? 1. voltage control circuit d/a converter amp in( ? ) amp out v lc1 v ss v ext v lc2 v lc3 v lc4 v lc5 v lcbs1 v lcbs2 v lcbs3 da cha amp in(+) r 1 r 2 c 1 ? + reference power supply circuit
data sheet s14207ej3v0ds 8 pd16681a 4. power supply circuit a switchable (3x or 4x) boost circuit is included to generate a current for driving the lcd. a connection to a boost- related capacitor is used to switch the boost circuit?s setting. the v ext pin (h: external, l: internal) is used to switch between using an external lcd driver power supply or the on-chip boost circuit. 4.1 boost circuit when using the internal power supply, connect the boost-related capacitor between c 1 + and c 1 ? , c 2 + and c 2 ? , and c 3 + and c 3 ? . also, connect the capacitor for level stabilization between v lcd and v ss , and set v ext low to boost the potential between v dd and v ss from 3 to 4 times. since the boost circuit uses signals from the internal oscillation circuit, the oscillation circuit must be operating. the relation between the boosted voltage and the potential is described below. the c 1 + to c 3 ? and v dd pins all relate to the boost circuit, so the wire impedance should be minimized. figure 4 ? ? ? ? 1. 3x and 4x boost mode v dd = 3 v v ss = 0 v v lcd = 3v dd = 9 v (during 3x boost mode ) v lcd = 4v dd = 12 v (during 4x boost mode) note note when set for 3x boost, connect boost-related capacitors between c 2 ? and c 3 + and c 1 + and c 1 ? .
data sheet s14207ej3v0ds 9 pd16681a 4.2 regulation of lcd driver voltage 4.2.1 when not using internal power supply select or d/a converter (v ext = l, da cha = l) when using the internal power supply, the boosted voltage is used as the power supply for the op amp incorporated in the ic for the lcd driver?s voltage. a common mode amplifier circuit can be configured by connecting external resistors r1 and r2 and inputting the reference voltage v ref to amp in(+) , and this configuration can be used to regulate the potential of the lcd driver voltage v lc1 . if using a thermistor to regulate the lcd driver voltage to suit the liquid crystals? temperature characteristics, we recommend connecting in parallel to r2. the lcd driver voltage v lc1 can be determined using the following formula. th 2 th 2 2 ref 1 2 out lc1 r r r r ' r v r ' r 1 amp v + = ? ? ? ? ? ? + = = figure 4 ? ? ? ? 2. when not using internal power supply select or d/a converter d/a converter amp in( ? ) amp out v lc1 r 2 r 1 c 1 r th amp in (+) v ref da cha to internal drive circuit + ? 4.2.2 when using internal power supply select and d/a converter (v ext = l, da cha = h) using the d/a converter enables commands to be entered to control the reference voltage v ref that is input to the + input of the op amp for the lcd driver voltage. the d/a converter function sets 6-bit data to the d/a converter set register to set one of the 64 modes for the reference voltage v ref between v dd and 1/2 v dd . the formula for v lc1 is the same as in 4.2.1 when not using internal power supply select or d/a converter (v ext = l, da cha = l) above. remark
data sheet s14207ej3v0ds 10 pd16681a figure 4 ? ? ? ? 3. using internal power supply select and d/a converter v dd d/a converter amp in( ? ) amp out v lc1 r 2 r 1 c 1 + ? r th amp in(+) da cha open v ref v dd to internal drive circuit 4.2.3 when using an external power supply (v ext = h) when an external power supply is used for the lcd driver voltage, the op amp incorporate in the pd16681a (used for the lcd driver voltage) is in off mode. consequently, the lcd driver?s op amp and d/a converter function cannot be used when using an external power supply. instead, regulate the lcd driver voltage by inputting directly to the v lcd and v lc1 pins. cautions 1. maintain the following relation for the voltage input to the v lcd and v lc1 pins : v lcd > v lc1 2. since the da cha , amp in(+) , and amp in( ? ? ? ? ) pins are cmos inputs, they should be fixed either high or low. 3. the amp out pin should be left unconnected. 4.3 reference voltage 4.3.1 when using internal power supply (v ext = l) when using the internal power supply, the pd16681a?s on-chip divider resistor is used to create the six-level potential (v lc1 to v lc5 , and v ss ) required for the lcd driver. 4.3.2 when using an external power supply (v ext = h) when use of an external power supply has been selected, the op amp incorporated in the pd16681a for the lcd driver level power supply is in off mode, so a reference potential must be directly input to v lc1 to v lc5 . ordinarily, these levels are generated by dividing the resistance. since large resistance values result in poorer lcd display quality, be sure to select a resistance value that suits the type of lcd panel to be used. the display quality can be improved by connecting capacitors between the level pins and ground pins. as with the resistance values described above, the capacitance values of the capacitors should be selected to suit the divided resistance values and the type of lcd panel to be used.
data sheet s14207ej3v0ds 11 pd16681a 4.4 control of op amp for level power supply input to the amp cha pin is used to control the op amp for the lcd driver level power supply. ? high power mode (amp cha = l) this mode maximizes the lcd drive current supply capacity in the op amp for the lcd driver level power supply. ? normal mode (amp cha = h) this mode uses a lower lcd drive current supply capacity in the op amp for the lcd driver level power supply, which is suitable for charging the capacitor used to stabilize the external level. caution for either mode, be sure to connect a level stabilization capacitor (rated from about 0.1 to 1.0 f) for the v lc1 to v lc5 pins. poorer display quality results when these capacitors are not connected. figure 4 ? ? ? ? 4. reference voltage circuit v lc1 r output to seg and com v lc2 r v lc3 r r 2r v lcbs3 v lcbs2 v lc4 r v lc5 r amp out v lcbs1 v ss op amp for level driver + ? + ? + ? + ? + ? output to seg and com output to seg and com output to seg and com output to seg and com output to seg and com
data sheet s14207ej3v0ds 12 pd16681a 4.5 bias value settings the bias value can be set as 1/6 bias, 1/7 bias, or 1/8 bias by selecting an internal bias for the ( pd16681a and by connecting externally from the ic among v lcbs1 -v lcbs3 pins. bias value connected pin 1/8 bias v lcbs1 -v lcbs3 leave open 1/7 bias between v lcbs1 and v lcbs2 or between v lcbs2 and v lcbs3 1/6 bias between v lcbs1 and v lcbs3 and v lcbs2 leave open 4.6 power supply circuit use example figure 4 ? ? ? ? 5. using internal power supply and normal mode v dd to v dd v lcd c 1 c 1 c 2 c 2 c 3 c 3 v ss v lc5 v lc4 v lc3 v lc2 v lc1 amp out amp ( ?) amp (+) v ext r 2 r th (thermistor) r 1 c 2 c 1 c 1 c 1 v dd v lcd c 3 open v cha v ss v ext c 2 c 1 + + + + amp cha v dd c 1 c 2 c 3 open c 2 c 1 c 1 + + + + + + + + + + ? + ? + ? ? + + ? ? + a) 4x boost (d/a converter is not used.) b) 3x boost remarks 1. c 1 = 1.0 f, c 2 = 1.0 f 2. leave c 2 + and c 3 ? pins open during 3x boost. 3. leave amp (+) open when using the d/a converter.
data sheet s14207ej3v0ds 13 pd16681a figure 4 ? ? ? ? 6. using external power supply circuit v dd c 1 c 1 c 2 c 2 c 3 c 3 v ss v lc5 v lc4 v lc3 v lc2 open v lc1 v lcd amp out open amp ( ? ) amp (+) v ext v dd r r 4r r r + ? + ? + ? to external drive supply a) use 1/8 bias remark fix all open input pins high or low.
data sheet s14207ej3v0ds 14 pd16681a 5. lcd display driver either a 1/52 duty driver or a 1/39 duty driver can be selected for the pd16681a. both drivers output a drive waveform using the two-frame ac drive method. 5.1 1/52 duty driver when the 1/52 duty driver is selected for the pd16681a, a select signal is output once per frame from the dot block?s common outputs (com 1 to com 51 ) and from the pictograph block?s common outputs (same signal output from pcom 1 and pcom 2 ). figure 5 ? ? ? ? 1. 1/52 duty driver v lc1 v lc2 v lc3 seg 1 com 1 com 2 pcom 1 pcom 2 v lc4 v lc5 v ss v lc1 v lc2 v lc3 v lc4 v lc5 v ss v lc1 v lc2 v lc3 v lc4 v lc5 v ss v lc1 v lc2 v lc3 v lc4 v lc5 v ss 1frame 1234567 5051521234567 50 51 52 8 8
data sheet s14207ej3v0ds 15 pd16681a 5.2 1/39 duty driver when the 1/39 duty driver is selected for the pd16681a, a select signal is output once per frame from the dot block?s common outputs (com 1 to com 19 , com 27 to com 45 ) and from the pictograph block?s common outputs (same signal output from pcom 1 and pcom 2 ). figure 5 ? ? ? ? 2. 1/39 duty driver v lc1 v lc2 v lc3 seg 1 com 1 com 2 pcom 1 pcom 2 v lc4 v lc5 v ss v lc1 v lc2 v lc3 v lc4 v lc5 v ss v lc1 v lc2 v lc3 v lc4 v lc5 v ss v lc1 v lc2 v lc3 v lc4 v lc5 v ss 1frame 1234567 3738391234567 37 38 39 8 8
data sheet s14207ej3v0ds 16 pd16681a 6. description of blocks 6.1 display data ram (ddram) ddram is ram that contains display data consisting of a 16-bit character code plus a character attribute code. the ram capacity is 16 x 72 bits, which means that up to 72 characters can be stored in ram. the following table shows correspondences between ddram addresses and lcd display positions. for further description of these correspondences, see the section 7.1 lcd display and ddram addresses. 123456789101112131415161718 1st line 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 2nd line 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 3rd line 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 4th line 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh 40h 41h 42h 43h 44h 45h 46h 47h 6.2 full width (11x12 dots) character generator rom (fcgrom) fcgrom generates a total of 6,808 full width character patterns, of which 6,355 are jis level 1 + level 2 kanji, and 453 are non-kanji characters. these character patterns are displayed in 11 x12 dot font patterns based on 12-bit character codes. the section entitled 7.2.2 full width(11 x 12 dots) character code setting examples describes the correspondence between the character codes set to ddram and this full width font pattern. also, see the section entitled 7.2 character codes for a description of the correspondence between the jis code and the character code set to ddram. 6.3 half width(5 x 12 dots) character generator rom (hcgrom) fcgrom generates a total of 192 half width (5 x 12 dots) character patterns, displayed in 5 x 12 dot font patterns. the section entitled 7.2 character codes describes the correspondence between the character code set to ddram and the half width font patterns.
data sheet s14207ej3v0ds 17 pd16681a 6.4 character generator ram (cgram) cgram is ram to which the user can freely set character patterns. eight types of 12 x 13 dot character patterns can be defined. to display a character pattern that has been stored in cgram, the user specifies a value ranging from ?000h? to ?007h?. the relation between character codes and cgram addresses used to access cgram is shown below. figure 6 ? ? ? ? 1. the relation between character codes and cgram addresses d 7 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a d 6 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a d 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 d 4 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 d 3 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 d 2 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 0 d 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 d 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 d 7 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a d 6 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a d 5 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 d 4 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 0 d 3 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 d 2 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 d 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 a2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 a3 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 a4 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 a5 0 1 1 a6 0 0 1 a7 0 0 1 c0 0 1 1 c1 0 0 1 c2 0 0 1 c3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c12 0 0 0 0 0 0 to cgram data a0 ="0" a0 ="1" cgram address character code 0 0 0 0 0 0 0 0 0
data sheet s14207ej3v0ds 18 pd16681a remarks 1. cgram is selected when the high-order nine bits (c11 to c3) of a character code are all zeros. at that time, the low-order three bits (c2 to c0) corresponds to cgram addresses 7 to 5 (a7 to a5). (three bits: eight types.) 2. display on is selected when the cgram data value is ?1?. display off is selected when this data value is ?0?. 3. the cgram address 0 (a0) corresponds to the left and right sides of the character pattern. 4. the high-order two bits of cgram are used to control the display attributes of the pattern corresponding to the low-order six bits. in such cases, any display attribute specification made for ddram is ignored. when the value of the high-order two bits is ?00?, cgram?s pattern is displayed. 5. cgram addresses 4 to 1 (a4 to a1) corresponds to the line position of the character pattern. (four bits : 13 lines) the ored result with the cursor is taken and displayed on the 12th line. 6.5 pictograph display ram (pdram) pdram is the ram that contains pictograph display data that has been assigned to pcom 1 and pcom 2 . the data display function is on when the data value is ?1? and off when the data value is ?0?. after data is written, the address counter is automatically incremented (by one), and the value after 0fh is 00h. the correspondence between output from various segments and pdram addresses is shown below. pcom 1 , pcom 2 segment output no. address b7 b6 b5 b4 b3 b2 b1 b0 00h xx654321 01h x x 12 11 10 9 8 7 02h x x 18 17 16 15 14 13 03h x x 24 23 22 21 20 19 04h x x 30 29 28 27 26 25 05h x x 36 35 34 33 32 31 06h x x 42 41 40 39 38 37 07h x x 48 47 46 45 44 43 08h x x 54 53 52 51 50 49 09h x x 60 59 58 57 56 55 0ah x x 666564636261 0bh x x 727170696867 0ch x x 787776757473 0dh x x 848382818079 0eh x x 908988878685 0fh x x 969594939291 remark x: don?t care
data sheet s14207ej3v0ds 19 pd16681a 6.6 pictograph blink data ram (pbram) pbram is the ram that contains pictograph blink data that has been assigned to pcom 1 and pcom 2 . a data value of ?1? is written to the address of the pictograph to be set for a blink display. after data is written, the address counter is automatically incremented (by one), and the value after 0fh is 00h. the correspondence between output from various segments and pbram addresses is shown below. pcom 1 , pcom 2 segment output no. address b7 b6 b5 b4 b3 b2 b1 b0 00h xx654321 01h x x 12 11 10 9 8 7 02h x x 18 17 16 15 14 13 03h x x 24 23 22 21 20 19 04h x x 30 29 28 27 26 25 05h x x 36 35 34 33 32 31 06h x x 42 41 40 39 38 37 07h x x 48 47 46 45 44 43 08h x x 54 53 52 51 50 49 09h x x 60 59 58 57 56 55 0ah x x 666564636261 0bh x x 727170696867 0ch x x 787776757473 0dh x x 848382818079 0eh x x 908988878685 0fh x x 969594939291 remark x : don?t care 6.7 relation between addresses and various rom and ram devices the pd16681a assigned fcgrom addresses as shown below to hcgrom and cgram. type no. of characters address range jis kanji 6,355 same as kanji rom ic non-jis kanji 453 same as kanji rom ic half width alphanumeric characters 192 uses addresses 0080h to 039fh in the kanji rom ic cgram 8 uses addresses 0000h to 0007h in the kanji rom ic
data sheet s14207ej3v0ds 20 pd16681a 7. lcd display the pd16681a?s lcd display can display four lines containing up to 8 characters (11 x 12 dots) or 16 characters (5 x 12 dots) and 96 pictographs. 1 2 3 seg pcom 1 pcom 2 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 16 com 17 com 18 com 19 com 47 com 48 com 49 com 50 com 51 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 85 86 87 88 89 90 91 92 93 94 95 96 remark the same select signal is output from pcom 1 and pcom 2 .
data sheet s14207ej3v0ds 21 pd16681a 7.1 lcd display and ddram addresses the character code used in the pd16681a contains 16 bits (character code + character attribute code). when data is stored to an address in ddram, a combination of full width (11 x 12 dots) and half width (5 x 12 dots) characters can be displayed on the lcd. the relation between the ddram?s character area and the actual lcd display when displaying a combination of full width and half width characters is shown below. figure 7 ? ? ? ? 1. the relation between the ddram?s character area and the actual lcd display lcd display note note half width space ddram 123456789101112131415161718 1st line 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 2nd line 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 3rd line 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 4th line 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh 40h 41h 42h 43h 44h 45h 46h 47h remark shaded areas indicate addresses. address characters that are not displayed are used as data for character scrolling.
data sheet s14207ej3v0ds 22 pd16681a 7.2 character codes the pd16681a is able to combine full width characters (11 x 12 dots) and half width characters (5 x 12 dots) in the same display. the character data that is stored in ddram is displayed starting from the top left corner of the lcd screen. a one-dot character interval is added to the left of each character font. both full width (11 x 12 dots) and half width (5 x 12 dots) characters are handled using 16-bit code lengths and are stored in ddram. the 16-bit code format uses the low-order 13 bits as the character code. the remaining 3 bits are the high-order 3 bits, which specify the character width (full or half) and the display attribute. the msb is the select bit indicating full width or half width character code: ?0? specifies full width characters and ?1? specifies half width characters. the character attribute code is assigned to the next two bits, and can specify attributes such as blinking for individual characters. (see the section 7.3 display attributes .) 7.2.1 code format d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 f/h a1 a0 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 full width(11 x 12 dots) character/ half width(5 x 12 dots) character specification display attribute codes high-order character code low-order character code 7.2.2 full width (11 x 12 dots) character code setting examples the following shows the correspondence between 16-bit jis code and the pd16681a?s 13-bit character code. this correspondence varies according to the values of the high-order 3 bits (b17, b16, and b15) in the first byte of the jis code. convert jis code as shown below to generate character code for the pd16681a. (1) jis level 1 kanji and non-kanji characters table 7 ? ? ? ? 1. when (b17, b16, b15) = (0, 1, 0) first byte second byte jis c 6226 b17 b16 b15 b14 b13 b12 b11 b27 b26 b25 b24 b23 b22 b21 character code c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 remark c12 = c6 = c5 = 0 table 7 ? ? ? ? 2. when (b17, b16, b15) = (0, 1, 1) or (1, 0, 0) first byte second byte jis c 6226 b17 b16 b15 b14 b13 b12 b11 b27 b26 b25 b24 b23 b22 b21 character code c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 remark c12 = 0
data sheet s14207ej3v0ds 23 pd16681a (2) jis level 2 kanji and non-kanji characters table 7 ? ? ? ? 3. when (b17, b16, b15) = (1, 1, 1) first byte second byte jis c 6226 b17 b16 b15 b14 b13 b12 b11 b27 b26 b25 b24 b23 b22 b21 character code c9 c8 c7 c11 c10 c4 c3 c2 c1 c0 remark c12 = 1, c6 = c5 = 0 table 7 ? ? ? ? 4. when (b17, b16, b15) = (1, 0, 1) or (1, 1, 0) first byte second byte jis c 6226 b17 b16 b15 b14 b13 b12 b11 b27 b26 b25 b24 b23 b22 b21 character code c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 remark c12 = 1 (3) cgram d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0xx00000 00000u2u1u0 remark cgram addresses for user font: u2 to u0
data sheet s14207ej3v0ds 24 pd16681a 7.3 display attributes in the pd16681a, the character code is assigned to 12 bits of the 16-bit data that is specified as full width (11 x 12 dots) characters or half width (5 x 12 dots) characters and the display attribute code is assigned to two of the remaining four bits. normal display or blink display mode can be specified for each character unit. the blink cycle for blink display mode is 64 frames, so that display blinks on or off once every 32 frames. 7.3.1 character code format d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 f/h a1 a0 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 full width(11 x 12 dots) character/ half width(5 x 12 dots) character specification display attribute codes high-order character code low-order character code 7.3.2 display attribute specifications a1 a0 display mode 0 0 normal display 0 1 reverse display 1 0 character blink 1 1 reverse character blink 7.3.3 display examples (1) normal display (2) reverse display
data sheet s14207ej3v0ds 25 pd16681a (3) blink display display alternates once every 32 frames (4) reverse blink display display alternates once every 32 frames
data sheet s14207ej3v0ds 26 pd16681a 8. commands 8.1 basic format + + + + command register (cr) command register (cr) extended selection register (esr) address register (ar) ram address register (rad) command register (cr) note data 1(dt1) note the command (1 or 2 bytes) immediately follows the falling edge of the stb signal, and whatever is sent after that is recognized as data. table 8 ? ? ? ? 1. command list register contents command b7 b6 b5 b4 b3 b2 b1 b0 reset 00100411 display on/off 00001b2b1b0 standby 00010b2b1b0 duty setting 000110b1b0 cursor control 000111b1b0 d/a converter setting 00101000 scroll control 0011b3b2b1b0 blink setting 010000b1b0 address register 010010b1b0 data r/w mode 10110b2b1b0 test mode 1010b3b2b1b0 8.1.1 reset this command resets all of the commands in the pd16681a. msb lsb 0 0 1 0 0 0 1 1
data sheet s14207ej3v0ds 27 pd16681a 8.1.2 display on/off this command controls the display?s on/off status. msb lsb selection 000 : lcd off (seg n , com n , pcom n = v ss ) 001 : lcd off (seg n , com n , pcom n = non-select waveform) 111 : lcd on 0 0 0 0 1 b2 b1 b0 8.1.3 standby this command stops the dc/dc converter, which reduces the supply current. the display is set to off mode (seg n , com n = v ss ). msb lsb 0 0 0 1 0 b2 b1 b0 selection 000 : normal operation 001 : standby (stop dc/dc converter, fulll display off ,stop osc) note note seg n , com n , pcom n = v ee 8.1.4 duty setting this command specifies the duty setting. msb lsb 0 0 0 1 1 0 b1 b0 selection 00 : 1/52 duty 01 : 1/39 duty note note use com 1 to com 19 and com 27 to com 45 , leave com 20 to com 26 and com 46 to com 51 open when setting 1/39 duty.
data sheet s14207ej3v0ds 28 pd16681a 8.1.5 cursor control this command controls the cursor?s on/off status. msb lsb 0 0 0 1 1 1 b1 b0 selection 00 : cursor off 10 : cursor on (no blink) 11 : cursor on (blink) note2 note1 note3 notes 1. 00: sets cursor to off mode. 2. 10: sets cursor to on mode (cursor is displayed). the cursor is displayed at the character which occupies the display position of the currently specified ddram address. the ?address register? + ?data r/w command? combination is used to set data to ddram addresses. when accessing ram, the address counter in ram is automatically incremented (+1) or decremented ( ? 1), and the cursor is moved accordingly. 3. 11: this sets the cursor to on mode and causes the cursor to blink. the blink cycle is 64 frames. the correspondence between the cursor and the ram address is the same as when the cursor is blinking. caution the cursor display function is valid only when the display attribute specifies ?normal display? (a0 = 0, a1 = 0). 8.1.6 d/a converter set 1 the d/a converter?s output for the lcd driver is set in 64 steps from v dd to 1/2 v dd . msb lsb 0 0 b5 b4 b3 b2 b1 b0 msb lsb 0 0 1 0 1 0 0 0 + extended selection d/a output selection 00h(min.) to 3fh(max.) remark this value is set to 20h after a reset.
data sheet s14207ej3v0ds 29 pd16681a 8.1.7 scroll control this controls scrolling of displayed characters. the individual bits in the selection are allocated to their respective display lines. when the data value is ?1?, scrolling is enabled for that line. the distance of the dots? leftward (horizontal) motion is selected via the extended selection register that is input after the command. the dot move distance varies depending on the current lcd display status and the contents of ddram. for details, see the section 8.4 scrolling . msb lsb 0 b6 b5 b4 b3 b2 b1 b0 msb lsb 0 0 1 1 b3 b2 b1 b0 + selection b0 : scroll selection on fourth line b1 : scroll selection on third line b2 : scroll selection on second line b3 : scroll selection on first line dot move distance selection 8.1.8 pictograph blink setting this command performs blink control for the pictograph at addresses where the blink (pbram) data value is ?1?. msb lsb 0 1 0 0 0 0 b1 b0 selection 00 : stop blink (blink frequency = f osc /319488) 01 : stop blink (blink frequency = f br1 /2) 10 : start blink (blink frequency = f osc /319488) 11 : start blink (blink frequency = f br1 /2) note note note this refers to the frequency of the external clock that is input from the osc br1 pin.
data sheet s14207ej3v0ds 30 pd16681a 8.1.9 data r/w command this command performs data read/write operations. msb lsb b7 b6 b5 b4 b3 b2 b1 b0 msb lsb 1 0 1 1 0 b2 b1 b0 + + selection 1 00 : increments up from the current address 01 : retains current address 10 : decrements down from the current address note 1 note 1 selection 2 0 : data write 1 : data read note 2 notes 1. during increment mode, when the current address is the last address the next address becomes 00h. during decrement mode, when the current address is 00h, the next address becomes the last address. 2. data read mode is cancelled at the rising edge of the stb signal (mode is switched to command/data write mode). caution during a serial data transfer, write data in 8-bit or 16-bit segments. if the rising edge of stb occurs during the data transfer operation, the operation is not guaranteed. 8.1.10 test mode this command sets the test mode. the test mode is only for confirming the ic?s operation. regular or continuous use while in test mode is not guaranteed. msb lsb 1 0 1 0 b3 b2 b1 b0 selection 0000 : normal operation 0001 to 1111 : test mode
data sheet s14207ej3v0ds 31 pd16681a 8.2 address register this command selects the address type and specifies addresses. msb lsb b7 b6 b5 b4 b3 b2 b1 b0 msb lsb 0 1 0 0 1 0 b1 b0 + selection 1 00 : ddram address 01 : pdram address 10 : pbram address 11 : cgram address selection 2 ddram address : 00h to 47h pdram address : 00h to 0fh pbram address : 00h to 0fh cgram address : 00h to f9h caution operation is not guaranteed if an invalid address is set. 8.3 reset the contents of the various registers appear as shown below after a reset (command reset or hardware [pin] reset). register contents command b7 b6 b5 b4 b3 b2 b1 b0 description display on/off 00001000lcd off (seg n , com n , pcom n = v ss ) standby 0 0010000normal operation duty setting 000110001/52 duty cursor control 00011100cursor off d/a converter setting00101000set to 20h scroll control 00110000no specified scroll line blink setting 01000000blink stop address register 01001000ddram is specified data r/w mode 10110000data write/increment (+1) test mode 10100000normal operation
data sheet s14207ej3v0ds 32 pd16681a 8.4 scrolling character scrolling is controlled by inputting scroll control commands (8 bits) plus scroll dot count data (8 bits). the line to be scrolled is specified by the scroll control command and the scroll dot count data sets the number of dots to be scrolled. when this command is input, the characters on the specified line are shifted leftward by the specified number of dots. the number of dots that can be scrolled differs according to the contents of the data stored in ddram (for details, refer to 8.4.1 scrollable number of dots and 8.4.2 display and scrollable number of dots ). consequently, if scrolling is specified for an amount of data that exceeds the scrollable data, the character data, only the scrollable data is shifted and overwritten, and scrolling must be performed again. caution for character scrolling, be sure to input a scroll control command (8 bits) plus the amount of scrolled data (8 bits). 8.4.1 scrollable number of dots scroll amount = (12 dots x number of non-displayed full width characters that are stored in ddram) + (6 dots x number of non-displayed half width characters that are stored in ddram) 8.4.2 display and scrollable number of dots lcd display: ddram status 123456789101112131415161718 1st line 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 2nd line 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 3rd line 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 4th line 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh 40h 41h 42h 43h 44h 45h 46h 47h remark shaded areas indicate addresses. address characters that are not displayed are used as data for character scrolling.
data sheet s14207ej3v0ds 33 pd16681a character memory contents remarks 1. shaded areas indicate addresses. 2. first line: (10 full width (11 x 12 dots) characters) second line: (6 full width (11 x 12 dots) characters), "484" ? (4 half width (5 x 12 dots) characters) third line: "pb"(2 half width (5 x 12 dots) characters) fourth line: (2 full width (5 x 12 dots) characters) scrollable dot counts; first line: (12 dots x 10 characters) + (6 dots x 0 characters) = 120 dots second line: (12 dots x 6 characters) + (6 dots x 4 characters) = 96 dots third line: (12 dots x 0 characters) + (6 dots x 2 characters) = 12 dots fourth line: (12 dots x 2 characters) + (6 dots x 0 characters) = 24 dots if scroll count data that exceeds the scrollable number of dots is entered using the scroll control command, all dots that are in the area that goes beyond the ddram addresses are output as off data.
data sheet s14207ej3v0ds 34 pd16681a 8.5 serial communication format (1) reception 1 (command write, 1 byte) stb data b7 b6 b5 b2 b1 b0 sck 123 678 (2) reception 2 (command/data write, 2 bytes or more) stb data sck 12 command 1 command 1/data wait time t wait 3 678 12345 b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3 (3) transmission (command/data read) stb data sck 123 678 12345 b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3 6 data read command setting wait time t wait data read
data sheet s14207ej3v0ds 35 pd16681a 8.6 parallel communication format (1) 8-bit parallel interface stb d 0 - d 7 e
data sheet s14207ej3v0ds 36 pd16681a 9. command examples table 9 ? ? ? ? 1. initial setting (1/39 duty) + data input stbd7d6d5d4d3d2d1d0 status hard reset hxxxxxxxx l 0 0 0 1 1 0 0 1 duty setting (1/39 duty) hxxxxxxxx l 0 1 0 0 1 0 0 0 address register (ddram address selection) 0 0 0 0 0 0 0 0 ddram address: 00h hxxxxxxxx 1 0 1 1 0 0 0 0 data write, address is incremented starting from current address d15 d14 d13 d12 d11 d10 d9 d8 data for first character d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 data for second character d7 d6 d5 d4 d3 d2 d1 d0 : d15 d14 d13 d12 d11 d10 d9 d8 data for 54th character l d7 d6 d5 d4 d3 d2 d1 d0 hxxxxxxxx l 0 1 0 0 1 0 0 1 address register (pdram address selection) h 0 0 0 0 0 0 0 0 pdram address: 00h lxxxxxxxx 1 0 1 1 0 0 0 0 data write, address is incremented starting from current address x x d d d d d d pdram: data at 00h x x d d d d d d pdram: data at 01h : l x x d d d d d d pdram: data at 0fh hxxxxxxxx 0 1 0 0 1 0 1 0 address register (pbram address selection) l 0 0 0 0 0 0 0 0 pbram address : 00h hxxxxxxxx 1 0 1 1 0 0 0 0 data write, address is incremented starting from current address x x d d d d d d pbram: data at 00h x x d d d d d d pbram: data at 01h : l x x d d d d d d pbram: data at 0fh hxxxxxxxx l00001111display on hxxxxxxxx to next processing remark x: don?t care
data sheet s14207ej3v0ds 37 pd16681a table 9 ? ? ? ? 2. cgram data write stbd7d6d5d4d3d2d1d0 status start hxxxxxxxx 0 1 0 0 1 0 1 1 address register (cgram address selection) l 0 0 0 0 0 0 0 0 cgram address: 00h hxxxxxxxx 1 0 1 1 0 0 0 0 data write, address is incremented starting from current address a a d5 d4 d3 d2 d1 d0 data for first character (at 000h) a a d5 d4 d3 d2 d1 d0 data in first line of pattern a a d5 d4 d3 d2 d1 d0 data for first character (at 000h) a a d5 d4 d3 d2 d1 d0 data in second line of pattern : a a d5 d4 d3 d2 d1 d0 data for xth character (at 00mh) l a a d5 d4 d3 d2 d1 d0 data in nth line of pattern hxxxxxxxx to next processing remark x: don?t care
data sheet s14207ej3v0ds 38 pd16681a 10. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol rating unit supply voltage (4x boost) v dd ? 0.3 to +3.75 v supply voltage (3x boost) v dd ? 0.3 to +5.0 v driver supply voltage v lcd ? 0.3 to +15.0, v dd v lcd v driver reference supply input voltage v lc1 -v lc5 ? 0.3 to v lcd +0.3 v logic system input voltage v in1 ? 0.3 to v dd +0.3 v logic system output voltage v out1 ? 0.3 to v dd +0.3 v logic system input/output voltage v i/o1 ? 0.3 to v dd +0.3 v driver system input voltage v in2 ? 0.3 to v lcd +0.3 v driver system output voltage v out2 ? 0.3 to v lcd +0.3 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 55 to +150 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol min. typ. max. unit supply voltage (4x boost) v dd 2.0 3.0 v supply voltage (3x boost) v dd 2.0 4.0 v driver supply voltage v lcd 5.0 10 12 v logic system input voltage v in 0v dd v driver system input voltage v lc1 -v lc5 0v lcd v remarks 1. when using an external power supply, be sure to maintain these relations: v ss < v lc5 < v lc4 < v lc3 < v lc2 < v lc1 v lcd 2. maintain v dd v lcd when turning the power on or off. 3. keep voltage input to the amp in(+) pin between 1.0 v and v dd when using an internal power supply but not using the d/a converter.
data sheet s14207ej3v0ds 39 pd16681a electrical characteristics (unless otherwise specified, t a = ? ? ? ? 40 to +85 c, v dd = 2.0 to 3.0 v during 4x boost mode or 2.0 to 4.0 v during 3x boost mode) parameter symbol condition min. typ. max. unit high-level input voltage v ih 0.8 v dd v low-level input voltage v il 0. 2v dd v high-level input current i ih1 except for d 0 /data and d 1 to d 7 1 a low-level input current i il1 except for d 0 /data and d 1 to d 7 ? 1 a high-level output voltage v oh i out = ? 1.0 ma, except osc out v dd ? 0.5 v low-level output voltage v ol i out = 2.0 ma, except osc out 0.5 v high-level leakage current i loh d 0 /data and d 1 to d 7 , v in/out = v dd 10 a low-level leakage current i lol d 0 /data and d 1 to d 7 , v in/out = v ss ? 10 a common output on resistance r com v lcn com n, v lcd 3v dd , i lol = 50 a2k ? segment output on resistance r seg v lcn seg n, v lcd 3v dd , i lol = 50 a4k ? driver voltage (boost voltage) v lcd during 3x boost 2.7 v dd 3.0 v dd v during 4x boost 3.6 v dd 4.0 v dd v current consumption (normal mode) i dd11 f osc = 375 khz, all display off data output, v dd = 3.0 v during 3x boost mode 100 180 a f osc = 375 khz, all display off data output, v dd = 3.0 v during 4x boost mode 135 210 a current consumption (high-power mode) i dd12 f osc = 375 khz, all display off data output, v dd = 3.0 v during 3x boost mode 150 280 a f osc = 375 khz, all display off data output, v dd = 3.0 v during 4x boost mode 200 340 a driver system current consumption (v dd ) (standby) i dd21 v dd = 3.0 v 1 10 a remark the typ. value is a reference value when t a = 25 c test circuit d/a converter da cha amp in( ? ) amp out v lc1 v lc2 v lc3 v lc4 v lc5 v ss v ext + ? v dd amp in(+) reference supply circuit
data sheet s14207ej3v0ds 40 pd16681a switching characteristics (unless otherwise specified, t a = ? ? ? ? 40 to +85 c) v dd = 2.0 to 2.7 v parameter symbol conditions min. typ. max. unit oscillation frequency f osc self-oscillation, oscillation resistance r = 100 k ? 180 500 khz transfer delay time t phl sck data 150 ns transfer delay time t plh sck data 150 ns remark the typ. value is a reference value when t a = 25 c v dd = 2.7 to 3.3 v parameter symbol conditions min. typ. max. unit oscillation frequency f osc self-oscillation, oscillation resistance r = 100 k ? 240 378 560 khz transfer delay time t phl sck data 60 ns transfer delay time t plh sck data 60 ns remark use the following equation to determine the time per frame. 1 frame = 1/f osc x 96 x number of duty f osc = 375 khz, given a 1/52 duty, 1 frame = 2.67 s (96 x 52 = 13.1 ms ? 75 hz)
data sheet s14207ej3v0ds 41 pd16681a required timing conditions (unless otherwise specified, t a = ? ? ? ? 40 to +85 c) common (1) (v dd = 2.0 to 2.7 v) parameter symbol conditions min. typ. max. unit clock frequency f osc osc in external clock 375 khz high-level clock pulse width t whc1 osc in external clock 1000 ns low-level clock pulse width t wlc1 osc in external clock 1000 ns high-level clock pulse width t whc2 osc bri external clock 1000 ns low-level clock pulse width t wlc2 osc bri external clock 1000 ns rise/fall time tr,tf osc bri external clock 100 ns reset pulse width t wre /reset pin 100 s reset cancellation time t rre /reset pin 100 s remark the typ. value is a reference value when t a = 25 c common (2) (v dd = 2.7 to 3.3 v) parameter symbol conditions min. typ. max. unit clock frequency f osc osc in external clock 240 375 560 khz high-level clock pulse width t whc1 osc in external clock 500 ns low-level clock pulse width t wlc1 osc in external clock 500 ns high-level clock pulse width t whc2 osc bri external clock 400 ns low-level clock pulse width t wlc2 osc bri external clock 400 ns rise/fall time t r ,t f osc bri external clock 100 ns reset pulse width t wre /reset pin 50 s reset cancellation time t rre /reset pin 50 s remark the typ. value is a reference value when t a = 25 c serial interface (1) (v dd = 2.0 to 2.7 v) parameter symbol conditions min. typ. max. unit shift clock cycle t cyk sck 2000 ns high-level shift clock pulse width t whk sck 1000 ns low-level shift clock pulse width t wlk sck 1000 ns shift clock hold time t hstbk stb sck 300 ns data setup time t ds1 data sck 150 ns data hold time t dh1 sck data 150 ns stb hold time t hkstb sck stb 300 ns stb pulse width t wstb 300 ns wait time t wait 8th sck 1st sck 1000 ns remarks 1. the typ. value is a reference value when t a = 25 c 2. t.b.d. (to be determined.)
data sheet s14207ej3v0ds 42 pd16681a serial interface (2) (v dd = 2.7 to 3.3 v) parameter symbol conditions min. typ. max. unit shift clock cycle t cyk sck 500 ns high-level shift clock pulse width t whk sck 260 ns low-level shift clock pulse width t wlk sck 210 ns shift clock hold time t hstbk stb sck 260 ns data setup time t ds1 data sck 40 ns data hold time t dh1 sck data 40 ns stb hold time t hkstb sck stb 260 ns stb pulse width t wstb 210 ns wait time t wait 8th sck 1st sck 260 ns remark the typ. value is a reference value when t a = 25 c parallel interface (1) (v dd = 2.0 to 2.7 v) parameter symbol conditions min. typ. max. unit enable cycle time t cyce e e 2000 ns high-level enable pulse width t whe e 1000 ns low-level enable pulse width t wle e 1000 ns stb pulse width t wstb 300 ns stb hold time t wkstb 300 ns enable hold time t hstbk 300 ns data setup time t ds2 d 0 to d 7 e 150 ns data hold time t dh2 d 0 to d 7 e 150 ns remark the typ. value is a reference value when t a = 25 c parallel interface (2) (v dd = 2.7 to 3.3 v) parameter symbol conditions min. typ. max. unit enable cycle time t cyce e e 500 ns high-level enable pulse width t whe e 260 ns low-level enable pulse width t wle e 210 ns stb pulse width t wstb 210 ns stb hold time t wkstb 260 ns enable hold time t hstbk 260 ns data setup time t ds2 d 0 to d 7 e 40 ns data hold time t dh2 d 0 to d 7 e 40 ns remark the typ. value is a reference value when t a = 25 c
data sheet s14207ej3v0ds 43 pd16681a ac timing measurement voltages v ih input v il v oh output v ol ac characteristics waveforms osc in t whc1 t wlc1 1/f osc t whc2 t wlc2 osc vr1 t f t r serial interface (input) stb sck data t hstbk t hkstb t cyk t whk t wstb t ds1 t dh1 t wlk serial interface (output) sck data t phl t plh
data sheet s14207ej3v0ds 44 pd16681a 8-bit parallel interface t hstbk t wle t ds2 t dh2 t whe t cyce stb e d n t wkstb t wstb reset t wre /reset t rre reset time reset cancellation time
data sheet s14207ej3v0ds 45 pd16681a 11. character code tables (standard rom code, pd16681aw/p-001) the following tables show the correspondences between character codes and characters. character codes ranging from 0000h to 0007h are assigned to cgram. character allocation table (1) c12 = 0
data sheet s14207ej3v0ds 46 pd16681a character allocation table (2) c12 = 0
data sheet s14207ej3v0ds 47 pd16681a character allocation table (3) c12 = 0
data sheet s14207ej3v0ds 48 pd16681a character allocation table (4) c12 = 0
data sheet s14207ej3v0ds 49 pd16681a character allocation table (5) c12 = 1 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000001111111111111111 00000000111111110000000011111111 00001111000011110000111100001111 00110011001100110011001100110011 01010101010101010101010101010101 yo?????a????????e????? y !"#$%&'()*+,-./0123456 yvwxyz{|}~????????????????????? y?????yt?a????????e? y2345?yyyyyyyyyyyyyyyyyyyyyyyyy ?yt?a????????e????? 789:;<=>?@abcdefghijklmnopqrstuv ?????????????|?a??-?23 ?????yt?
?yt?
y wxyz[\]^_`abcdefghijklmnopqrstuy ??1o?????a????????e?y !"#$%&'()*+,-./01y c6 c5 c4 c3 c2 c1 c0 012345678910111213141516171819202122232425262728293031 c11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 c10 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 c9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 c8 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 c7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 maintenance area maintenance area maintenance area maintenance area
data sheet s14207ej3v0ds 50 pd16681a character allocation table (6) c12 = 1
data sheet s14207ej3v0ds 51 pd16681a character allocation table (7) c12 = 1
data sheet s14207ej3v0ds 52 pd16681a character allocation table (8) c12 = 1
data sheet s14207ej3v0ds 53 pd16681a [memo]
data sheet s14207ej3v0ds 54 pd16681a [memo]
data sheet s14207ej3v0ds 55 pd16681a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16681a reference documents nec semiconductor device reliability/quality control system (c10983e) semiconductor device mounting technology (c10535e) m8e 00. 4 the information in this document is current as of june, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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